● CLEANROOM BAY 04 · ISO CLASS 5 · LINK STABLE

Safiya builds chips that tape out clean.

ASIC physical design engineer — floorplan to GDSII on 7nm and 5nm FinFET. Six production tape-outs, zero respins from layout. This is her control room: press the button and watch a sign-off run close.

Run Verification Talk to Safiya

0production tape-outs

0layout-caused respins

0largest instance count

0highest signed-off clock

0in physical design

01 / SIGN-OFF

Live tape-out verification

A replay of ATLAS-7's final sign-off week, compressed to forty seconds. DRC, LVS, antenna and timing all have to reach zero before the GDSII leaves the building.

signoff.tcl — ATLAS-7_top IDLE

safiya@pd-farm-04:~/atlas7$ ▌

Speed

DRC VIOLATIONS14,382Calibre nmDRC · 2,104 rules

LVS MISMATCHES217Calibre nmLVS · 38.4M devices

ANTENNA96diode insertion · M1–M13

SETUP TNS-412.6 psPrimeTime SI · 27 corners

SIGN-OFF STATUSAWAITING RUN

LVS NET TRACE · layout ⇄ schematic0 / 0 nets matched

WORST SLACK ACROSS PVT CORNERSWNS setup —

02 / CORNERS

PVT corner matrix

Every chip has to work at every combination of process skew, supply voltage and junction temperature. Pick a cell to see its numbers, then push the knobs yourself.

DELAY ON CRITICAL PATH (ps) · cpu_core/alu/mul_stage3target 312 ps @ 3.2 GHz

meets target under 5% margin violates — needs fix

CORNER CALCULATORTT · 0.75V · 25°C

Process Voltage 0.75 V Temperature 25 °C Clock 3.20 GHz Switching activity 0.18

Path delay—

Setup slack—

Dynamic power—

Leakage—

Total power—

Energy / cycle—

delay ∝ V / (V − V_th)^α · α = 1.3 · P_dyn = a·C·V²·f · leakage doubles every ~22 °C

03 / FLOW

RTL to GDSII, stage by stage

Safiya's FinFET implementation flow. Click any stage to open what happens there, which tool runs it and the numbers she watches. Press “Trace” to send a netlist through the whole hierarchy.

flow.graph

mermaid · ECO loop between sign-off and implementationsequence

sequenceDiagram
    participant PT as PrimeTime STA
    participant S as Safiya
    participant INV as Innovus
    participant CAL as Calibre
    PT->>S: 37 setup violators at SSG 0.675V -40C
    S->>S: Sort by path group, pick sizing vs. buffering
    S->>INV: ecoChangeCell + ecoAddRepeater (TCL)
    INV->>INV: ECO route, 0.3% wire change
    INV->>CAL: Stream out GDS + LEF/DEF
    CAL-->>S: DRC 0, LVS clean
    S->>PT: Re-run with StarRC SPEF
    PT-->>S: WNS +4.1 ps, all corners met

04 / SANDBOX

Place the macros yourself

A 1.2 × 1.2 mm block with six SRAM macros and an I/O ring. Drag macros to shorten wires and clear congestion. Keep-out halos must not overlap, and the hotspot grid updates as you move.

floorplan.def · blk_l2cacheDRAG A MACRO

05 / TOOLBENCH

EDA tools and benchmarks

Runtimes from her own runs on ATLAS-7 (38M instances, 64-core farm nodes). The table is her daily kit; the charts show where the hours go.

RUNTIME PER STAGE (hours)before → after her TCL tuning

PROFICIENCY RADARself-rated, 0–10

TOOL MATRIXclick a header to sort

QoR TREND ACROSS TAPE-OUTSutilisation % · WNS ps · power mW/MHz

06 / MISSION LOG

Tape-outs on record

07 / HANDOFF

Have a block that won't close timing?

Safiya takes on physical design roles and short sign-off rescues: floorplan reviews, congestion fixes, CTS tuning and the last mile of DRC. Send a note with your node and target date.